Geometrical optimizing design of interconnection for deep sub - micrometer vlsi circuits 電路中互連線的幾何優化設計
Most of vlsi circuits are sequential circuits . sequential circuits can be simulated by symbolic finite state machine ( fsm ) Vlsi系統中大部分是時序電路,時序電路可以用符號化的有限狀態機( finite - state - machine ,簡稱fsm )來模擬。
The design method of the circuits has the characteristics of systematization and modularization , so it suits the implementation of the vlsi circuit of the continuous wavelet transform system 這類電路的設計方法具有系統化、模塊化的特點,適合連續小波變換系統這樣的大規模電路的實現。
It details the ic design process and vlsi circuits , including gate arrays , programmable logic devices and arrays , parasitic capacitance , and transmission line delays 它詳細規定了集成電路設計過程和超大規模集成電路電路,包括門陣列,可編程邏輯器件和陣列,寄生電容,及輸電線路的延誤。
Test is an indispensable task of vlsi circuits design . with the increased complexity of vlsi circuits , time overhead of atpg has become a bottleneck of design 隨著vlsi電路復雜性的增長,自動測試生成( atpg , automatictestpatterngeneration )的時間開銷已經成為vlsi電路設計的瓶頸之一。